Sr. FPGA Engineer — R&D, High‑Speed Digital Systems (mmWave)

Senior FPGA Engineer — R&D, High‑Speed Digital Systems (mmWave)
Location: Tbilisi, Georgia
Position Type: Full‑Time | Founding Engineering Team

About RIVVOR:

RIVVOR is a next‑generation wireless systems company headquartered in Silicon Valley, with engineering hubs in Montréal, Canada, and Tbilisi, Georgia. We engineer terabit‑class wireless links that power AI supercomputers, quantum clusters, and interplanetary networks. Forged through close collaboration with national laboratories, elite universities, and deep‑tech enterprises, our team of semiconductor veterans transforms frontier RF science into infrastructure that moves data at the speed of thought.

About the Role:

As a Senior FPGA Engineer, you will design high‑performance digital pipelines for mmWave wireless systems, working across the full RTL development flow—from architecture and modeling through FPGA bring‑up and automated testing. This is a hands‑on R&D position focused on advanced DSP and ultra‑low‑latency data paths tightly integrated with hardware and system software. You’ll collaborate closely with system architects, RF designers, and software engineers to build the digital core of mmWave platforms.

What You’ll Do:

• Develop Verilog/SystemVerilog RTL for DSP and high‑speed digital modules

• Integrate and configure FPGA/SoC/RF‑SoC platforms (AMD/Xilinx, Intel, or equivalent)

• Implement PCIe/DMA pipelines with host system interfaces (Linux/Windows)

• Import Matlab/Python model parameters into HDL processing pipelines

• Build monitoring modules for latency, BER, throughput, SNR, and FEC performance

• Construct testbenches and simulation flows (ModelSim, Questa, Vivado, cocotb)

• Collaborate with Python/software engineers to integrate device drivers and automated tests

• Document architecture and contribute to design review discussions

Requirements:

• Proven FPGA/RTL design experience in Vivado, Quartus, or similar environments

• Strong Verilog and/or SystemVerilog skills, including DSP algorithm implementation (FIR, FFT, QAM, FEC, etc.)

• Experience with PCIe, AXI4, DMA engines, and high‑speed host memory architectures

• Expert-level simulation/test proficiency and testbench development

• Familiarity with UVM-based methods or cocotb/Python-based automation frameworks

• English language fluency (B2 or higher) for team communication

Bonus Qualifications:

• Board bring-up experience: power sequencing, diagnostics, initial hardware validation

• Exposure to JESD204, RF/DSP co-design, or SDR systems

• Programming experience in Python or C/C++ for automation or test flow

• Hardware-in-the-loop (HIL) experience or rigorous co-simulation using cocotb/Pytest

Tech Stack:

Verilog, SystemVerilog, Vivado, Quartus, ModelSim, Questa, cocotb, Python, MATLAB, PCIe, DMA/AXI4, FIR/FFT/FEC pipelines, SNR/BER throughput monitoring, Linux/Windows host environments, FPGA/SoC platforms

Why Join Us:

• Lead development of foundational digital subsystems in next-gen mmWave wireless platforms

• Collaborate with a global team of RF, silicon, and systems engineers

• Build pioneering infrastructure technology through mission-driven engineering

• Thrive in a culture rooted in deep technical expertise and fast execution