Sr. Lead FPGA/ASIC Engineer (mmWave)
Location: Tbilisi, Georgia
Position Type: Full-Time | Founding Engineering Team
Compensation: $100K-120K base + annual performance bonus + equity (stock options)
Visa & Relocation Support: Relocation support to Georgia, including work permits and legal assistance
About the Role
As a Senior/Lead FPGA/ASIC Engineer, you’ll lead the design and implementation of digital subsystems for our custom mmWave wireless chips. This includes everything from PHY/MAC engines to beamforming DSP blocks and real-time packet processing pipelines. You’ll work at the intersection of high-frequency RF, real-time digital signal processing, and embedded systems, owning the full digital path from RTL design to lab validation and silicon bring-up. This is a core founding engineering role with high ownership and cross-functional leadership responsibilities.
What You’ll Do
Architect and implement DSP blocks for mmWave PHY/MAC and beamforming subsystems
Lead RTL design in SystemVerilog/Verilog from spec through verification and integration
Develop real-time packet processors, filters, synchronizers, and adaptive equalizers.
Drive the FPGA prototyping path and guide the transition to ASIC implementation.
Collaborate with RF, embedded, and hardware system teams for seamless cross-domain integration.
Mentor junior engineers and establish best practices for verification and design flow.
Optimize for PPA (power, performance, area) in high-speed, low-latency applications.
Own lab bring-up, debugging, and system integration with RF front-end and firmware
What We’re Looking For
7+ years of FPGA/ASIC design experience in comms, DSP, or high-speed systems
Strong command of SystemVerilog, Verilog, and verification methodologies (UVM/VMM)
Deep experience with PHY/MAC design, OFDM, MIMO, AGC, SYNC, EQ, or packet processing
Proficiency in RTL design flows: synthesis, simulation, timing closure, bring-up
Experience with high-speed I/O (PCIe, SerDes, DDR, JESD204) and lab validation
Track record of leading digital projects from architecture to silicon
Strong leadership skills and experience managing 3+ engineers
Bonus: Background in mmWave systems, beamforming algorithms, or wireless ASICs
Tools & Tech
SystemVerilog • Verilog • Vivado • Quartus • ModelSim • UVM • TCL • Python • Cocotb • MATLAB/Simulink • Git • CI/CD pipelines
Why Join Us?
Lead Digital Architecture: Own the core logic behind a new class of wireless silicon
Compensation: $100-120K base + equity + milestone-based bonuses
World-Class Team: Collaborate with RF, systems, and hardware experts from top labs and companies
Mission-Driven: Build infrastructure for the age of ultra-high-speed, planet-wide connectivity
Benefits: Flexible schedule, wellness stipend, team offsites, relocation support, health insurance
